Our Engineers have been designing PLDs and FPGAs since 1990, growing a long experience with CAE tools, different HDL languages, simulation and verification tools and, most important, developing a strong knowledge of technology related limitations and requirements.

We have been working with Altera, Actel and Xilinx products from the smallest to the biggest devices for glue logic to complete chip simulation for ASIC design.

In our partnership with silicon manufacturers we've been contributing in chip design by designing portions of the RTL code, debugging and verifying it both in simulation and real world conditions.